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Publications

Publications#

Books#

Blogs#

Patents#

  • Granted US Patents
    • US 8,156,457, "Concurrent simulation of hardware designs with behavioral characteristics"
    • US 8,738,350, "Mixed concurrent and serial logic simulation of hardware designs"
  • Pending US Patents
    • 63/934,790, "Systems and Methods for Causal Failure Prediction in Time Series"
    • 63/960,355, "Computational Systems and Methods for Time Series Data Processing"

Papers#

2026#

  • C. Ma, G. Pomazkin, G.P. Saggese, P. Smith, Beyond Accuracy: A Stability-Aware Metric for Multi-Horizon Forecasting, arXiv preprint arXiv:2601.10863, 2026

2025#

  • G.P. Saggese, P. Smith, Causify Causal Technology Stack, Preprint, 2025

  • K. Taduri, S. Dhande, G.P. Saggese, P. Smith, Causify Benchmark: A Benchmark of Causal AI for Predictive Maintenance, arXiv preprint arXiv:2512.01149, 2025

  • G.P. Saggese, P. Smith, Causify DataMap: A Causal Probabilistic Reasoning, Preprint, 2025

  • G.P. Saggese, P. Smith, Causify DataFlow: A Causal Simulator for Stream Computing AI, arXiv preprint arXiv:2512.23977, 2025

  • G.P. Saggese, P. Smith, Causify DataPull: A Causal Data Layer for Time-series, Preprint, 2025

  • C. Ma, S. Nikiforova, G.P. Saggese, P. Smith, K. Taduri, Causify Sentinel: A Causal Failure Prediction Framework, Preprint, 2025

  • C. Ma, G.P. Saggese, P. Smith, Causify Grid: A Causal Inference in Energy Demand Prediction, arXiv preprint arXiv:2512.11653, 2025

  • C. Ma, G. Pomazkin, G.P. Saggese, P. Smith, D. Tikhomirov, N. Trubacheva, Causify Horizon: A Causal Demand Forecasting Framework, Preprint, 2025

  • G.P. Saggese, P. Smith, Causify Optima: The Effect of Latency on Optimal Order Execution Policy, arXiv preprint arXiv:2504.00846, 2025

  • G.P. Saggese, P. Smith, Causify: AIgentic Development System, Preprint, 2025

  • G.P. Saggese, P. Smith, Causify: A Full-Stack Causal AI Framework, Preprint, 2025

  • G.P. Saggese, P. Smith, Runnable Directories: The Solution to the Monorepo vs. Multi-repo Debate, arXiv preprint arXiv:2512.03815, 2025

2011#

  • K. Pattabiraman, G.P. Saggese, D. Chen, Z. Kalbarczyk, R.K. Iyer, Automated Derivation of Application-Specific Error Detectors Using Dynamic Analysis, IEEE Transactions on Dependable and Secure Computing, vol. 8, no. 5, pp. 640-655, 2011

2006#

  • K. Pattabiraman, G.P. Saggese, D. Chen, Z. Kalbarczyk, R.K. Iyer, Dynamic Derivation of Application-Specific Error Detectors and their Implementation in Hardware, Sixth European Dependable Computing Conference (EDCC 2006), Coimbra, Portugal, pp. 97-108, 2006

2005#

  • G.P. Saggese, N.J. Wang, Z. Kalbarczyk, S.J. Patel, R.K. Iyer, An Experimental Study of Soft Errors in Microprocessors, IEEE Micro, vol. 25, no. 6, pp. 30-39, 2005

  • G.P. Saggese, A. Vetteth, Z. Kalbarczyk, R.K. Iyer, Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic, 2005 International Conference on Dependable Systems and Networks (DSN 2005), Yokohama, Japan, pp. 760-769, 2005

  • N. Nakka, G.P. Saggese, Z. Kalbarczyk, R.K. Iyer, An Architectural Framework for Detecting Process Hangs/Crashes, Dependable Computing - EDCC-5, Budapest, Hungary, Lecture Notes in Computer Science, vol. 3463, pp. 103-121, Springer, 2005

  • A. Cilardo, A. Mazzeo, L. Romano, G.P. Saggese, Architecture and FPGA Implementation of a Digit-serial RSA Processor, New Algorithms, Architectures and Applications for Reconfigurable Computing, pp. 209-218, Springer, 2005

2004#

  • G.P. Saggese, L. Romano, N. Mazzocca, A. Mazzeo, A Tamper Resistant Hardware Accelerator for RSA Cryptographic Applications, Journal of Systems Architecture, vol. 50, no. 12, pp. 711-727, 2004

  • A. Cilardo, A. Mazzeo, L. Romano, G.P. Saggese, G. Cattaneo, A Web Services Based Architecture for Digital Time Stamping, Journal of Web Engineering, vol. 2, no. 3, pp. 148-175, 2004

  • A. Cilardo, A. Mazzeo, L. Romano, G.P. Saggese, Exploring the Design-Space for FPGA-Based Implementation of RSA, Microprocessors and Microsystems, vol. 28, no. 4, pp. 183-191, 2004

  • A. Cilardo, A. Mazzeo, L. Romano, G.P. Saggese, Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware, 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Paris, France, pp. 206-211, 2004

  • G.P. Saggese, C. Basile, L. Romano, Z. Kalbarczyk, R.K. Iyer, Hardware Support for High Performance, Intrusion- and Fault-Tolerant Systems, 23rd International Symposium on Reliable Distributed Systems (SRDS 2004), Florianópolis, Brazil, pp. 195-204, 2004

2003#

  • G.P. Saggese, Using Programmable Hardware to Improve the Dependability of Cryptographic Applications, PhD Thesis, University of Naples Federico II, Italy, 2003

  • A. Mazzeo, L. Romano, G.P. Saggese, N. Mazzocca, FPGA-Based Implementation of a Serial RSA Processor, 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), Munich, Germany, pp. 10582-10589, 2003

  • G.P. Saggese, A. Mazzeo, N. Mazzocca, A.G.M. Strollo, An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm, Field Programmable Logic and Application (FPL 2003), Lisbon, Portugal, Lecture Notes in Computer Science, vol. 2778, pp. 292-302, Springer, 2003

  • A. Cilardo, A. Mazzeo, L. Romano, G.P. Saggese, G. Cattaneo, Using Web Services Technology for Inter-enterprise Integration of Digital Time Stamping, On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops, Catania, Sicily, Italy, Lecture Notes in Computer Science, vol. 2889, pp. 960-974, Springer, 2003

  • D. Cotroneo, C. di Flora, A. Mazzeo, L. Romano, S. Russo, G.P. Saggese, Providing Digital Time Stamping Services to Mobile Devices, 9th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS Fall 2003), Anacapri (Capri Island), Italy, pp. 94-100, 2003

  • A. Mazzeo, L. Romano, G.P. Saggese, Providing Interoperable Time Stamping Services, Scuola Superiore, 2003

2002#

  • B. Di Martino, N. Mazzocca, G.P. Saggese, A.G.M. Strollo, A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations, Field-Programmable Logic and Applications (FPL 2002), Montpellier, France, Lecture Notes in Computer Science, vol. 2438, pp. 47-58, Springer, 2002

  • G.P. Saggese, A.G.M. Strollo, N. Mazzocca, D. De Caro, Shuffled Serial Adder: An Area-Latency Effective Serial Adder, Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), Dubrovnik, Croatia, pp. 607-610, 2002

2001#

  • A.G.M. Strollo, E. Napoli, D. De Caro, G.P. Saggese, A Reconfigurable 2D Convolver for Real-Time SAR Imaging, Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2001), Malta, pp. 741-744, 2001

  • D. De Caro, N. Mazzocca, E. Napoli, G.P. Saggese, A.G.M. Strollo, Test Pattern Generator for Hybrid Testing of Combinational Circuits, Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2001), Malta, pp. 745-748, 2001

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